Engineer must know the FPGA pin signal distribution principle

Today's FPGAs are becoming more and more complex, and the task of allocating signals to pins has been simple and now quite complex. The following guidelines for assigning signals to multipurpose pins help designers to consider signal assignments in advance and reduce the number of iterations based on the most and least constrained signal assignment principles.

There is a premise here that the designer has determined the target device range and model based on the approximate size and signal requirements of the design. For each of the following steps, the differential pair signal should be prioritized before considering the unipolar signal.

The first special signals are those that can only work on specific pins, which are normally referred to as serial I/O signals and global clock signals. Second, assign large and/or high-speed signal buses, especially those that span multiple banks or regions. If the bus requires a local clock, consider a library or region with more local clock pins and assign a local clock first.

If multiple I/O standards are used for FPGA devices, designers must also first consider mapping I/O signals to banks/regions. This step needs to be carefully considered because many I/O standards and reference voltages are not compatible. Some I/O standards require a reference voltage to be applied to a particular pin so that these pins are no longer usable for general use. Separating high-speed outputs from bi-directional signals can avoid simultaneous switching output noise (SSO) problems to a certain extent.

Third, the same basic rules in the second step are used to assign slower and less constrained buses, but not too much consideration for SSO and other issues. Fourth, the assignment of individual signals is finally completed. If only a small number of pins are left, or if all the pins are used up in the first iteration, consider using the next device with more I/Os, because certain functions will definitely be added temporarily depending on market conditions. And no designer is willing to do the assignment process again in the final stages of design.

In each of the above steps, a constraint file with the correct signal assignment and I/O standards, and an HDL file containing the I/O design portion are created. Then start the layout and routing, because the error can be better found in the order from the most constrained signal to the least constrained signal.

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