Introduction to 22 common concepts about ARM
1. Some common English abbreviations in ARM
MSB: the most significant bit;
LSB: least significant digit;
AHB: Advanced high performance bus;
VPB: VLSI peripheral bus that connects on-chip peripheral functions;
EMC: external memory controller;
MAM: memory acceleration module;
VIC: vector interrupt controller;
SPI: full duplex serial interface;
CAN: Controller LAN, a serial communication protocol;
PWM: pulse width modulator;
ETM: embedded tracking macro;
CPSR: current program status register;
SPSR: Program Protection Status Register;
2.MAM usage precautions:
A: When changing the MAM timing value, you must first close the MAM by writing a 0 to the MAMCR and then write the new value to MAMTIM. Finally, write the corresponding value of the desired operating mode to the MAMCR and open the MAM again.
For system clocks below 20MHz, MAMTIM is set to 001. For system clocks between 20MHz and 40MHz, it is recommended to set the Flash access time to 2cclk, while at system clocks above 40MHz, 3cclk is recommended.
3.VIC Usage Precautions
A: If the code is running in on-chip RAM and the application needs to call an interrupt, then the interrupt vector must be remapped to Flash address 0x0. This is done because all exception vectors are located at address 0x0 and above. This is achieved by configuring the register MEMMAP (located in the system control module) to the user RAM mode. The user code is concatenated to load the interrupt vector table to 0x4000 0000.
4. ARM boot code design
A: The ARM boot code is programmed directly to the processor core and hardware controller, typically using assembly language. The startup code generally includes:
Interrupt vector table
Initialize the memory system
Initialize the stack to initialize ports and devices with special requirements
Initialize the user program execution environment
Change processor mode
Call the main application
5. The difference between IRQ and FIQ
A: IRQ and FIQ are two programming modes for ARM processors. IRQ refers to the interrupt mode and FIR refers to the fast interrupt mode. For FIQ you have to deal with your business as soon as possible and leave this mode. IRQ can be interrupted by FIQ, but IRQ cannot interrupt FIQ. In order to make FIQ faster, this mode has more shadow registers. FIQ cannot call SWI (software interrupt). FIQ must also disable interrupts. If an FIQ routine must re-enable interrupts, it is too slow and should be IRQ instead of FIQ.
6. ARM processor response process to abnormal interrupt
A: The response process of the ARM processor to the abnormal interrupt is as follows:
Saving the current state of the processor, the interrupt mask bit, and each condition flag bit;
Setting the corresponding bit in the current program status register CPSR;
Setting the register lr_mode to the return address;
The program counter value PC is set to the interrupt vector address of the abnormal interrupt, and jumps to the corresponding abnormal interrupt to execute.
7. The difference between ARM instructions and Thumb instructions
A: In the ARM architecture, the instructions in the ARM instruction set are 32-bit instructions, and their execution efficiency is very high. For applications where the storage system data bus is 16-bit, the ARM architecture provides the Thumb instruction set. The Thumb instruction set is recoded from a subset of the ARM instruction set, and the instruction length is 16 bits. Usually when the processor executes an ARM program, the processor is said to be in the ARM state; when the processor executes the Thumb program, the processor is said to be in the Thumb state. The Thumb instruction set does not change the programming model of the ARM architecture, but only imposes some restrictions on the model. The operand of the data processing instruction in the Thumb instruction set is still 32 bits, and the instruction addressing address is also 32 bits.
8. What is ATPCS?
A: In order to enable a separately compiled C language program and assembler to call each other, certain rules must be specified for calls between subprograms. ATPCS is the basic rule for subroutine calls in ARM programs and Thumb programs. These rules include register usage rules, usage rules for data stacks, and rules for passing parameters.
9. The occasion where the ARM program and the Thumb program are mixed.
A: Generally, Thumb programs are more compact than ARM programs, and for systems with 8 or 16 bits of memory, using Thumb programs is more efficient. However, in the following cases, the program must run in ARM state, then you need to mix ARM and Thumb programs.
Where speed is emphasized, the ARM program should be used;
Some functions can only be done by ARM programs. Such as: use or prohibit abnormal interruption;
When the processor enters the exception interrupt handler, the program state switches to the ARM state, that is, some instructions at the exception interrupt handler entry are ARM instructions, and then the program can switch to the Thumb state as needed, before the exception interrupt routine returns, the program Switch to the ARM state.
The ARM processor always executes from the ARM state. Therefore, if you want to run the Thumb program in the debugger, you must add an ARM program header to the Thumb program, then switch to the Thumb state and execute the Thumb program.
10.ARM processor operating mode
A: The ARM microprocessor supports 7 operating modes, which are:
User mode (usr): normal program execution state of the ARM processor;
Fast interrupt mode (fiq): for high speed data transfer or channel management;
External interrupt mode (irq): used for general purpose interrupt processing;
Management mode (svc): the protection mode used by the operating system;
Data Access Termination Mode (abt): Enter this mode when data or instruction prefetch is terminated for virtual storage and storage protection;
System mode (sys): Run a privileged operating system task;
Undefined Instruction Abort Mode (und): Enter this mode when an undefined instruction is executed, which can be used to support software emulation of the hardware coprocessor.
11. Exception types supported by the ARM architecture
A: The exceptions and specific meanings supported by the ARM architecture are as follows (the numbers in the circle indicate the priority):
Reset 1: When the reset level of the processor is valid, a reset exception is generated, and the program jumps to the reset exception (exception vector: 0x0000, 0000);
Undefined instruction 6: When the ARM processor or coprocessor encounters an instruction that cannot be processed, it is generated as a defined exception. This exception mechanism can be used for software simulation (exception vector: 0x0000, 0004);
Software Interrupt 6: There is an execution SWI instruction generated, which can be used in the user mode to call the privileged operation instruction. This exception mechanism can be used to implement system function calls (exception vector: 0x0000, 0008);
Instruction prefetch abort 5: If the address of the prefetch instruction of the processor does not exist, or the address does not allow access to the current instruction, the memory will issue an abort signal to the processor, and the prefetch will be generated when the prefetch instruction is executed. Abort exception (exception vector: 0x0000,000C);
Data abort 2: If the address of the instruction of the processor data access does not exist, or the address does not allow access to the current instruction, a data abort exception is generated (exception vector: 0x0000, 0010);
IRQ4 (External Interrupt Request): An IRQ exception is generated when the processor's external interrupt request pin is asserted and the I bit in the CPSR is '0'. The peripheral of the system can request the interrupt service (exception vector: 0x0000, 0018);
FIQ3 (Fast Interrupt Request): When the processor's fast interrupt request pin is valid and the F bit in the CPSR is 0, an FIQ exception (exception vector: 0x0000, 001C) is generated.
Description: The exception vector 0x0000, 0014 is the reserved exception vector.
12. ARM architecture memory format
A: The memory format of the ARM architecture has the following two types:
Big endian format: the high byte of the word data is stored in the low address, and the low byte of the word data is stored in the high address;
Little endian format: Contrary to the big endian storage format, the high address stores the high byte of the data and the low address stores the low byte of the data.
13. ARM register summary:
ARM has 16 32-bit registers (r0 to r15).
R15 acts as the program register PC, r14 (link register) stores the return address of the subroutine, and r13 stores the stack address.
ARM has a current program status register: CPSR.
Some registers (r13, r14) generate new instances when an exception occurs, such as IRQ processor mode, where the processor uses r13_irq and r14_irq
ARM subroutine calls are fast because the return address of the subroutine does not need to be stored on the stack.
For more information, please click on the following link: ARM Basics Summary
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